The present integrated circuit devices comprise a silicon substrate, doped regions in the semiconductor to which source or drain connections are made, separated by a gate control region. Metal connections to the source, gate, and drain electrodes are made by multilayer interconnects, which are supported over the substrate by an interlayer dielectric. To make electrical connection between different layers, the dielectric is sequentially patterned and etched to form contact and via openings. These opening are filled with plugs of an electrically conductive material such as tungsten, which contacts previously-doped regions, polysilicon, or other metal layers. A layer of PVD (physical vapor deposited) metal, i.e. TiN, is typically deposited on the sidewall of the contact/via openings to serve to structurally support the adhesion of the tungsten plug. The thickness of the TiN deposit typically ranges from 400 .ANG. or more (i.e., 1100 .ANG.) to maintain a thick enough TiN layer on the sidewalls to support the tungsten plug.
As device geometry gets smaller (.ltoreq.0.35 .mu.m) and contact/via aspect ratios (the ratio of height to diameter) become higher (close to 2.0 or higher), step coverage of the TiN becomes a concern. Due to concern about decreased step coverage, the TiN layer is required to be thick enough to guarantee adequate deposition within a contact. Current technology requires a thick enough TiN adhesion or "glue" layer for the blanket tungsten deposition on the contact and via levels to maintain good contact/via resistance. A minimum thickness of TiN on the contact level also serves as a barrier layer to protect junctions.
A need remains for a process which allows the use of very thin PVD TiN layers and eases concern about reduced step coverage.